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Making sense of the flags in /proc/cpuinfo - Nick [entries|archive|friends|userinfo]

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Making sense of the flags in /proc/cpuinfo [Jul. 28th, 2009|10:26 pm]
One issue you often face when trying to make sense of the flags given in /proc/cpuinfo is that all the interesting things you can google about a cpu feature are by their full name (eg Enhanced SpeedStep) and not by their flag (eg est). So, how do you turn the cryptic short form into the googlable long form?

The first thing to try is everyone's favourite "what's in my server" tool, dmidecode . With a new enough version, it'll decode a lot of the flags for you, eg
Processor Information
        Socket Designation: Microprocessor
        Type: Central Processor
        Family: Pentium M
        Manufacturer: Intel
        ID: E8 06 00 00 FF FB E9 BF
        Signature: Type 0, Family 6, Model 14, Stepping 8
                FPU (Floating-point unit on-chip)
                VME (Virtual mode extension)
                DE (Debugging extension)
                PSE (Page size extension)
                TSC (Time stamp counter)
                MSR (Model specific registers)
                PAE (Physical address extension)
                MCE (Machine check exception)
                CX8 (CMPXCHG8 instruction supported)
                APIC (On-chip APIC hardware supported)
                SEP (Fast system call)
                MTRR (Memory type range registers)
                PGE (Page global enable)
                MCA (Machine check architecture)
                CMOV (Conditional move instruction supported)
                PAT (Page attribute table)
                CLFSH (CLFLUSH instruction supported)
                DS (Debug store)
                ACPI (ACPI supported)
                MMX (MMX technology supported)
                FXSR (Fast floating-point save and restore)
                SSE (Streaming SIMD extensions)
                SSE2 (Streaming SIMD extensions 2)
                SS (Self-snoop)
                HTT (Hyper-threading technology)
                TM (Thermal monitor supported)
                PBE (Pending break enabled)

flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx constant_tsc arch_perfmon bts pni monitor vmx est tm2 xtpr pdcm

The slight snag is that it tends not to decode some of the more interesting and recent flags - notice above that my CPU supports EST (enhanced speedstep) and yet dmidecode hasn't mentioned it. If we go to a really new xeon cpu, with flags like:
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr lahf_lm
then the list of un-decoded bits is even longer.

For these outstanding flags that dmidecode doesn't know about, what you need is a recent set of linux kernel headers. Take a look in include/asm-i386/cpufeature.h (assuming your kernel is new enough to list all the flags that is!), you'll see things like:
#define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
#define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
#define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */

So, if we wanted to know what the est flag mean, we can see it's Enhanced SpeedStep, and google that (googling EST is largely unhelpful!). Likewise, we can see that the even more cryptic lahf_lm tells us LAHF and SAHF are enabled in 64 bit mode (long mode = 64 bit, as a few lines above explains), though you will still have to know that LAHF is a kind of cpu instruction...